The present invention relates to computer systems, and more particularly, to a configuration management subsystem of a computer system.
ACPI (Advanced Configuration and Power Interface) is an open industry specification that defines a flexible and extensible interface for computer system configuration and power management. The interface enables and supports power management through improved hardware and operating system coordination. ACPI allows the operating system to control the power states of many ACPI-compliant hardware components, and/or to pass information to and from some hardware components, such as the temperature of a thermal sensor or the power remaining in a battery.
During the boot process, an ACPI namespace is populated with software objects that are read from ACPI tables that are stored in an ACPI BIOS. Each hardware device in the machine has associated with it one or more of the objects in the ACPI namespace. As part of reading the ACPI tables and populating the ACPI namespace, often information is read from a CMOS device and placed temporarily in memory. For the purpose of the following discussion, the term xe2x80x9cCMOS devicexe2x80x9d means that portion of a computer having battery-backed storage, more specifically referred to as the PC-compatible Real Time Clock/CMOS Device. The typical CMOS device is the only place that computer firmware can store data that will not be lost even if the machine loses power. The typical CMOS device contains between 64 and 512 bytes of such non-volatile memory.
Because existing firmware systems do not provide safeguards on access to the CMOS devices, the information in memory may be easily corrupted if data is changed in the CMOS device while the data is also being read by another process. More specifically, the CMOS device is accessed through an indexed pair type mechanism. The CMOS device defines two separate and distinct registers. The first register (known as the index register) is used to define which offset in CMOS is desired. The second register (known as the data register) is used to access the data at the specified offset. To access CMOS properly, the index register must first be programmed with the desired offset, then the data is read from or written to the data register. A CMOS interleaved-access problem occurs if two pieces of code try to access the index and data register simultaneously. The following brief example best illustrates the problem:
1. Thread #1 attempts to read the contents of the CMOS device at Offset 0xc3x9713, so it writes 0xc3x9713 to the index register. However, before it has a chance to read from the data register, Thread #1 is preempted.
2. Thread #2 attempts to write 0xc3x97F3 to CMOS at Offset 0xc3x9720, so it writes 0xc3x9720 to the index register. However, before it has a chance to write to the data register, Thread #2 is preempted.
3. Thread #1 gets scheduled and runs again. It resumes from its last point of execution and reads the data from the data register. However, because the index register is now 0xc3x9720, the data is not the intended data, so it tries again and writes 0xc3x9713 to the index register. However, before it has a chance to read from the data register, Thread #1 is again preempted.
4. Thread #2 gets scheduled and runs again. It writes 0xc3x97F3 to the Data register, but since the index register is now 0xc3x9713, it wrote 0xc3x97F3 to the wrong offset.
5. Thread #1 runs again and reads from the data register, and gets the 0xc3x97F3.
As can be seen, interleaving accesses to the CMOS device can result in corruption. The simultaneous accesses to the CMOS device may be by two pieces of code in firmware, or may be between the firmware and the computer""s operating system. Existing firmware systems do not provide safeguards against such corruption. Thus, a need exists for a system and method for providing reliable access to a CMOS device by components interacting with a configuration management system.
Briefly stated, the present invention provides a system and method by which data accesses to information related to a CMOS device are synchronized by creating a special operation region through which the information is accessed. The invention defines an operation region of a new type from those available. More specifically, a xe2x80x9cCMOS Operation Regionxe2x80x9d is enabled through which the CMOS information is read or written. The memory within the CMOS device is typically composed of several disjoint 64-byte chunks, called xe2x80x9cbanks.xe2x80x9d The CMOS Operation Region presents an xe2x80x9caddress spacexe2x80x9d from 0 to N where N is the highest-numbered byte. The CMOS Operation Region abstracts the banks into the flat address space. AML that reads from or writes to a specific byte just refers to it by its offset in the address space.
When the AML interpreter performs a read or write instruction to the new operation region, the ACPI system passes that instruction to a process for handling that operation region, in this example the system kernel. The process may include mechanisms that synchronize accesses to the Operation Region so that a load or store operation is fully completed prior to allowing a subsequent load or store operation. In this way, the information associated with the CMOS device may be accessed in one atomic operation (i.e., not preemptable).
Other advantages will become apparent from the following detailed description when taken in conjunction with the drawings, in which: